‘Time-Triggered Reference Designs’ (TTRDs)


Our public ‘Time-Triggered Reference Designs’ (TTRDs) can be downloaded from this page.

Used in conjunction with the ‘ERES2‘ book, our public TTRDs are designed to illustrate ways in which TT software architectures can be used to support the development of a wide range of embedded systems for which safety is a key design consideration.

Use of these TTRDs is discussed in our Developers’ Blog.

[This page was last updated: 2017-03-06] empty_space


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ReliabiliTTy® Technology Licences

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The public TTRDs downloaded from this website may be used without charge: [i] by universities and colleges in courses for which a degree up to and including “MSc” level (or equivalent) is awarded; [ii] in non-commercial projects carried out by individuals and hobbyists.

Use of these TTRDs in any form of commercial project (including training courses) or in university research projects (including PhD-level programmes and equivalent) requires purchase of a ReliabiliTTy® Technology Licence.

Please contact us if you have any questions about these licence arrangements.
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TTRD2-02a [STM32-F091 target, Keil uVision project]

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Reviewing TTRD2-02a is a good way to begin exploring TT designs. This introductory design is documented in the sample chapters for the ERES2 book: these can be downloaded (free of charge) from the ERES2 page.

Latest version is ttrd2-02a-t0091a-v001c (zip file) [Release 2017-02-24a].

This TTRD targets an STM32F091RC MCU. It is designed to run on Nucleo-F091RC board. No external crystal assumed.

TTRD2-02a implements a simple ‘TTC’ scheduler design.

See ‘ERES2‘ Chapter 2 for details.

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TTRD2-03a [STM32-F401 target, Keil uVision project]

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Latest version is ttrd2-03a-t0401a-v001c (zip file) [Release 2017-02-24a].

This TTRD targets an STM32F401RE MCU. It is designed to run on a Nucleo-F401RE board. An external 16 MHz xtal is assumed to be present.

TTRD2-03a implements a simple TTC demo system with UART (Buffered Output) library.

Please see ‘ERES2‘ Chapter 3 for further information.

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TTRD2-03a [XMC4500 target, Keil uVision project]

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Latest version is ttrd2-03a-t4500a-v001c (zip file) [Release 2017-02-24a].

This TTRD targets an Infineon XMC4500 MCU. It is designed to run on a Relax Lite board.

TTRD2-03a implements a simple TTC demo system with UART (Buffered Output) library.

Please see ‘ERES2‘ Chapter 3 for further information.

NOTE: If you have v1 of the Relax Lite board, an FTDI interface (or similar) needs to be connected to Port 0, Pin 5 in order to see the UART outputs (because the ‘VCOM’ interface is not operational on this version of the board).

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TTRD2-04a [STM32-F401 target, Keil uVision project]

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Further information will be available shortly.
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TTRD2-05a [STM32-F401 target, Keil uVision project]

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Further information will be available shortly.
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TTRD2-09a [TMS570 target, TI CCS project]

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Further information will be available shortly.
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TTRD2-16a [STM32-F401 target, Keil uVision project]

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Further information will be available shortly.
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TTRD2-18a [STM32-F401 target, Keil uVision project]

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Further information will be available shortly.
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TTRD2-19a [STM32-F401 target, Keil uVision project]

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TTRD2-19a demonstrates a very popular TT software platform (‘CorrelaTTor’). Using an appropriate MCU and with the addition of a small external ‘watchdog’ device (eWDC), a CorrelaTTor platform can – for example – form the basis of an ‘ASIL D’ design (in compliance with ISO 26262).

We discuss this seminal TTRD on our Taster Days and during our TTb training course.

Latest version is ttrd2-19a-t0401a-v001b (zip file) [Release 2017-03-06a].

This TTRD targets an STM32F401RE MCU. It is designed to run on a Nucleo-F401RE board. An external 16 MHz xtal is assumed to be present.

TTRD2-19a implements a complete ‘CorrelaTTor-A’ platform. This includes a TTC scheduler plus iWDT, MoniTTor and PredicTTor mechanisms.

Please note that TTRD2-19a uses task timing data that were created using TTRD2-a07a (see below).

Please note that TTRD2-19a also uses task-sequence data that were created using TTRD2-a08a (see below).

Optionally, TTRD2-19a performs system resets every few seconds. The reset process involves repeating all of the core ‘Power On Self Tests (POSTs). Before performing the reset, part of the Processor state is stored: the state is recovered after the tests and the system continues. This type of periodic reset is sometimes employed in designs that must operate in very ‘hostile’ environments (e.g. with high levels of EMI or radiation).

Please see ‘ERES2’ Chapter 19 and Appendix 3 for further information about this TTRD.

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TTRD2-20a [TMS570 target, TI CCS project]

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Further information will be available shortly.
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TTRD2-a07a [STM32-F401 target, Keil uVision project]

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TTRD2-a07a is a key example for many TT development teams. This TTRD implements an ‘instrumented’ scheduler (based on TTRD2-19a in this example, but it can be adapted to any design). The example supports measurement of task execution-time (‘WCET’ and ‘BCET’) as well as measurements of ‘tick jitter’.

Latest version is ttrd2-a07a-t0401a-v001a (zip file) [Release 2017-03-06a].

This TTRD targets an STM32F401RE MCU. It is designed to run on a Nucleo-F401RE board. An external 16 MHz xtal is assumed to be present.

Please see ‘ERES2‘ Appx 07a and Chapter 19 for further information.
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TTRD2-08a [STM32-F401 target, Keil uVision project]

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TTRD2-a08a is another key example for TT development teams. This TTRD implements a ‘Dry Scheduler’: this type of project is used to generate ‘Tick Lists’. For example, the configuration presented here can be used to generate the Tick List that is employed by the PredicTTor mechanism in TTRD2-19a.

Latest version is ttrd2-a08a-t0401a-v001a (zip file) [Release 2017-03-06a].

This TTRD targets an STM32F401RE MCU. It is designed to run on a Nucleo-F401RE board. An external 16 MHz xtal is assumed to be present.

Please see ‘ERES2‘ Appendix 8 for further information.

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Are the TTRDs from ‘ERES1’ still available?

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You will find the TTRDs from ERES1 here.
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